The memory devices are driven by the new application and the requirement of the future. The advance in the field of computer and communications will use large quantities of each species of memories. For example, computer interfaces will become to be operated by speech processing or vision processing, and other communication interfaces, all of which require a lot of memories. Memory technology will continue to move in the direction of increased numbers of devices in a wafer. Read only memory (ROM) devices include ROM cells for coding data and a periphery controlling devices to control the operation of the cells. Each bit of data is stored in a cell, which is a single n-channel transistor or ROM cell. As well known in the art, the programming of the ROM is executed by controlling a threshold voltage of the MOS transistors constructing the memory cell by the implantation of dopant.
In general, mask ROM includes devices with difference threshold voltages. A type of device is formed in an active area and another type of device with a threshold voltage mask formed in another active area during the process. In MOS transistors for mask ROM, the threshold voltages of the channel regions under the gates are set to the same before data writing. Thereafter, ions are selectively implanted into determined regions to differentiate the threshold voltages thereof for data writing. One of the methods that involves differentiating the threshold voltages is achieved by ion implantation of some of the transistor gates. This method raises the threshold voltage of the n-channel device by doping boron with heavy dose. The prior arts relating to the ROM can be seen in U.S. Pat. No. 5,372,961 and U.S. Pat. No. 5,538,906 disclosed by Noda and Aoki, respectively. The process of ion implantation having high dose boron through the sacrifice oxide or the polysilicon gate into the substrate is widely used to fabricate the normally off mask ROM devices.
However, the high dose boron implantation results in a lower junction breakdown voltage of the coded MOS and more importantly to a very high leakage current between the adjacent bit lines. As mentioned in a U.S. Pat. No. 5,597,753 disclosed by Sheu, the high leakage current results in very high standby current. Another problem occurs with the ROM code implantation. As known in the art, after the code implantation is carried out, a thermal process is used to activate the implanted dopant which will cause counter doping of the adjacent bit lines, thereby increasing the bit line resistance and substantially degrading the performance of the ROM devices. One prior art to reduce the bit line resistance is disclosed by Hong in U. S. Pat. No. 5,571,739.